Solid state bulk memory is constructed by assembly arrays of semiconductor devices connected in parallel to common address leads, common input/output leads, and other common circuitry. Typically, one finds several hundred devices mounted on one plug-in card. If the devices have, say, sixteen thousand memory cells each, the card has about a half a megabit capacity.
In the prior art, data is stored and retrieved one word at a time. Typical prior art word lengths range from eight to sixty-four bits. For ease of description an eight bit word size is used for comparison herein. If a word length of eight bits is being used, the writing of data involves choosing a row and column address, presenting that address over the common circuitry to all of the devices, and enabling a certain group of eight devices on the card so that one bit of the word is stored in each device. If even one bit is incorrectly stored, problems arise when the word is later read out for use by the system. Accordingly, it has always been an objective of the prior art to have absolutely perfect memory devices in which every one of the thousands of memory cells on each device works reliably within a standardized set of parameters. This means that extensive testing must be performed on memory devices before they can be sold to users. The testing is expensive. And despite very high quality controls used in the manufacturing process, significant fractions of the devices do not pass the tests and must be rejected, thus lowering yields and increasing costs even more.
So far, the only way known to partially avoid this problem is to resurrect a few of the rejected devices in which only one or two bad memory cells exist in a known part of the device. If the bad cells are in just one area of the device, the bad area can be identified and the devices sold as "half good", "three-quarter good", or "one-quarter good" devices. These parts are then used as good parts of smaller size, the bad areas being avoided totally.
It would be very beneficial if a way could be found to utilize memory devices that were less than perfect, since the consistent production of perfect devices is unlikely to ever be attainable. To do this effectively, however, a wider range of partially defective memory devices should be usable, not just those that can be classified as "half good" or "quarter good." It is also desirable to be able to correct for additional bad memory cells that develop in the future. The present invention achieves these ends.